1. Field of the Invention
This invention relates generally to electronic test methods and more particularly to methods of testing for faults in a group of electronic components that provide digital signals indicative of component status.
2. Description of the Related Art
Numerous techniques have been developed to test for faults in digital portions of electronic devices. These techniques typically involve applying a suitable pattern of logical "1's" and "0's" to digital components of a device and then monitoring output signals from the components. For example, see U.S. Pat. No. 4,061,908. The problem of testing the components becomes considerably more difficult if the output signals cannot be readily accessed with external test equipment because the lines carrying the signals are "buried" in the device. In particular, the limited pin count of a typical large-scale packaged integrated circuit (IC) severely restricts the observability of the internal state of the IC.
Foster et al, "Checking Associative Store Address Line Drivers," IBM Tech. Disc. Bull., May 1971, pp. 3867-3868, describe one approach to overcoming this difficulty in testing line drivers that control pairs of address lines to a memory. The line drivers are tested for faults with a NAND gate responsive to output signals from test cells that form an extra memory.
A disadvantage of Foster et al is that a significant amount of on-chip test circuitry is needed to perform their test procedure. Furthermore, it depends on the existence of opposite binary signals on each pair of address lines during normal operation. It is desirable to have a more general method in which only a small amount of on-board test circuitry is needed to test for faults in a set of electronic components whose output signals are not readily accessible.